By Hammad M. Cheema, Reza Mahmoudi, Arthur H.M. van Roermund

The promising excessive information cost instant purposes at millimeter wave frequencies mostly and 60 GHz specifically have won a lot awareness lately. besides the fact that, demanding situations with regards to circuit, format and measurements in the course of mm-wave CMOS IC layout need to be triumph over sooner than they could turn into workable for mass market.

60-GHz CMOS Phase-Locked Loops targeting phase-locked loops for 60 GHz instant transceivers elaborates those demanding situations and proposes ideas for them. The method point layout to circuit point implementation of the full PLL, in addition to separate implementations of person elements equivalent to voltage managed oscillators, injection locked frequency dividers and their combos, are incorporated. additionally, to fulfill a couple of transceiver topologies concurrently, flexibility is brought within the PLL structure through the use of new dual-mode ILFDs and switchable VCOs, whereas reusing the low frequency elements on the comparable time.

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60-GHz CMOS Phase-Locked Loops

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Agilent’s Advanced Design System (ADS) provides an adequate tool-box for PLL related simulations. The loop’s AC response to extract stability information like phase margin, dynamic behavior to obtain settling time, and noise performance are all possible using this tool. A basic simulation environment is depicted in Fig. 11. The LPF block is custom-made based on the second order loop filter equations. The divider is used to step the division ratio and VCO output is demodulated using the FM_Demod block to obtain the settling time results.

1 This reflects the first major problem with mm-wave layout as l/10 factor is equal to 146 mm which can potentially be in the same order as the circuit dimensions. This means that firstly, RF interconnects carrying the high frequency signals should be as short as possible, secondly, the long interconnects should be realized as transmission lines (T-lines) having a controlled impedance and termination, and thirdly, the interconnects in the vicinity of above dimensions have to be treated in a distributed fashion involving meticulous calculations or electromagnetic (EM) simulations.

Therefore, small discontinuities (patterns) in the ground shield are introduced to reduce these eddy current loops to smaller area thereby lowering the cancellation effect. In addition, there is less magnetic field penetration into the substrate resulting in reduction of substrate losses. A few examples of patterned ground shields are shown in Fig. 6a–c. The drawback of the shield method is the possible reduction of self-resonance frequency (FSR) of the inductor caused by the increased capacitance.

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